Full-System Architectural Exploration Sandbox

The hardware realism and execution performance from prototyping using Field-Programmable Gate Arrays (FPGA) help address the key shortcomings of simulationbased computer architecture research. Although FPGA speed and capacity are approaching a pivotal threshold, creating a microarchitecturally-accurate FPGA prototype of a modern microprocessor remains at the limit of feasibility. On the other hand, an architecturally-accurate FPGA prototype to facilitate the examination of architecture design issues (e.g., new protection and memory models) is well within our reach. We present our plan to develop a fully-functional IA32 platform (Fig. 1) for architectural exploration where the processor and memory controller are implemented using FPGAs (CPU and M.C. FPGAs in Fig. 1). The malleable FPGA implementations of the processor and memory controllers will allow us to study architectural design changes that are impossible to emulate using commercial off-the-shelf (COTS) components. At the same time, this sandbox will deliver the necessary speedup, over software-simulation, to test new architectural concepts against real OS and applications. Below, we first give an overview of the planned exploration sandbox. Second, we highlight our current effort to develop an executable IA32 architectural model in FPGA for this sandbox.